1. Field of the Invention
The present invention relates generally to a package substrate and fabrication method thereof, and more specifically, to a package substrate and fabrication method thereof that forms an interposer and internal circuits on the surface of the substrate.
2. Description of the Prior Art
For the needs of achieving miniature sizes and high density in semiconductor packages, a three dimensional package technology such as through-silicon via (TSV) package technology is developed. Through-silicon via (TSV) package technology can effectively increase the three dimensional density, enabling the growing rate of semiconductor industry to exceed Moore's law. The level of through-silicon via (TSV) package technology is L/S (line width/line pitch) being less than 6/6. The cost of using a silicon substrate is four times that of using a flip chip ball grid array (FCBGA) substrate.
In consideration of the cost, there is a need in this industry to apply the FCBGA package technology in the art of three-dimensional packages to replace expensive TSV package technology. However, some problems will occur. First, present semi-additive process (SAP) still can not form these package products with a line-space scale of L/S<6/6. Second, the difference in the thermal expansion coefficient (CTE) of dielectrics applied in the IC carrier industry and the silicon substrate is too large, thereby the problem of reliability may occur. Otherwise, the layout of ultra high density interposer would be retrained by the processing limitation of solder resist opening(SRO)>65 um. Based on the current level of technology, the dimension of a blind hole in a substrate needs to be larger than 40 μm, thus circuit layout space may be wasted.
Therefore, a package substrate and fabrication method thereof, that can solve the aforesaid problems, is needed in the industry.